1. Technical Field
The present invention relates to a system and method for dynamic power management in a processor design. More particularly, the present invention relates to a system and method for using a stall condition to instruct idle detection logic to gate off register clocks within a pipeline stage in order to conserve power.
2. Description of the Related Art
Computer system designs incorporate a multitude of design approaches in order to achieve maximum performance. Once such design approach is pipelining. A pipeline is an implementation technique whereby multiple instructions are overlapped in execution. Pipelines may be segmented into “stages,” whereby each stage includes one or more instruction units or execution units. A pipeline stage includes a “stall point,” which is a location in the pipeline that checks for a stall condition. For example, a pipeline stage may include an issue unit, whereby the issue unit checks for stalls that correspond to an instruction waiting to issue.
Pipeline stall conditions result from a variety of reasons, such as executing a non-pipeline instruction, entering single-step mode, executing a de-normalization instruction, or identifying a data hazard. Stall conditions drive a corresponding pipeline stage into a stall state, and many of these stall conditions may last for an extended period of time.
Some processor designs incorporate software and hardware power management techniques to control pipeline stages. An example of software power management is for software to program a processor to switch from full power mode to sleep mode or slow mode. An example of hardware power management is to disable an individual pipeline when it is in an idle state. A challenge found, however, is that when a pipeline stage stalls, the pipeline is still considered an “active” pipeline and, therefore, neither software nor hardware power management gates off the pipeline's clocks.
What is needed, therefore, is a system and method to efficiently conserve power when a pipeline stage detects a stall condition.